It is difficult to form membranes with very small or thin dimensions using current techniques. First, the mechanical strength of porous nano-crystalline Si (pnc-Si) membranes may be limited to freely suspended areas under approximately 1 mm2 if the pnc-Si membrane is exposed to differential pressures exceeding 5 psi. 5 psi may represent a differential pressure that a pnc-Si membrane is likely to survive during an exemplary device assembly. Membrane deformation, such as that which occurs during exposure to certain differential pressures, is one factor that affects mechanical failure. Second, while chips with active areas as large as 1 cm2 can be manufactured using multiple windows and scaffolding, the cost of such chips is too expensive for many commercial applications. This is at least partly due to the number of chips that can be placed on a wafer. In an instance, nearly half the cost of wafer production could be attributed to the time and cost of the etch step through the Si to expose the membrane from the backside. Chemical etch through a Si wafer to reach the membrane backside is the costliest step in current membrane production.
Increasing ultrathin nanocrystalline silicon membrane area, such as those thinner than approximately 100 nm, through improvements in mechanical properties may be limited to freestanding areas of less than 10 mm2. Thus, large area membrane devices may require multiple membrane windows, which increases the cost per device as the fraction of the wafer that is occupied by each device increases. Methods that reduce the cost of membrane production may be needed if larger membranes are to become commercially viable. What is needed is an improved porous membrane and an improved method of making or using such a porous membrane.